EP20K400GC655-2V vs EP20K400GC655-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2V sa pamamagitan ng Altera at EP20K400GC655-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K400GC655-2V | EP20K400GC655-2X |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX-20KC | APEX-20KC® |
| Family | APEX 20KC (1.8 V, LVDS) | APEX 20K |
| Logic Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212992 |
| System Gates | ~400,000 (typical marketing figure) | 400000 |
| Number of I/O | [DATA_NEEDED: I/O count] | 496 |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | — |
| Process Technology | CMOS, 0.18 um | 0.22 µm CMOS |
| LVDS Support | Yes | — |
| Packhaging | 655-CPGA (62.48 x 62.48 mm) | — |
| Package Type | Ceramic Pin Grid Array, through-hole | 655-BCPGA (SPGA655) |
| Uri ng Pagpapasok | Through-hole (CPGA) | Through-hole (CPGA) |
| Speed Grade | -2 | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: temperature grade] |
| Tindminan RoHS | unknown | unknown |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Logic Elements / Cells | — | 16640 |
| Number of Dedicated Inputs | — | 6 |
| Number of LABs/CLBs | — | [DATA_NEEDED: number of Logic Array Blocks] |
| Number of EABs | — | [DATA_NEEDED: number of Embedded Array Blocks] |
| Maximum Operating Frequency | — | 200 MHz |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5 V |
| Package Body Material | — | CERAMIC, metal-sealed cofired grid array |
| Package Dimensions | — | 47 x 47 mm |
| Peak Reflow Temperature | — | 220 °C |
| Programmability | — | In-system, JTAG (IEEE 1149.1) |