EP20K400GC655-2X vs EP20K400GC655-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2X sa pamamagitan ng Altera at EP20K400GC655-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GC655-2X | EP20K400GC655-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX 20K | APEX 20K |
| Series | APEX-20KC® | APEX-20KC |
| Logic Elements / Cells | 16640 | — |
| System Gates | 400000 | — |
| Total RAM Bits | 212992 | 212992 |
| Number of I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Maximum Operating Frequency | 200 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | — |
| Package Type | 655-BCPGA (SPGA655) | — |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | — |
| Package Dimensions | 47 x 47 mm | — |
| Peak Reflow Temperature | 220 °C | — |
| Uri ng Pagpapasok | Through-hole (CPGA) | — |
| Programmability | In-system, JTAG (IEEE 1149.1) | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | -40C to +85C (industrial) |
| Tindminan RoHS | unknown | [DATA_NEEDED: rohs status] |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements | — | 16640 |
| Number of Gates | — | 400000 |
| Supply Voltage - Core | — | 1.71 V to 1.89 V (1.8 V nominal) |
| I/O Voltage Tolerance | — | MultiVolt I/O: 1.8 V / 2.5 V / 3.3 V / 5 V |
| Maximum Frequency | — | 167 MHz (per FPGAkey) |
| Packhaging / Kaso | — | 655-BCPGA |
| Supplier Device Package | — | 655-CPGA (62.48 x 62.48 mm) |
| Speed Grade | — | -3 (slowest grade in family) |
| Propagation Delay (tPD) | — | 3.6 ns (per Microchip USA listing) |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |
| Configuration Modes | — | Passive Serial, Passive Parallel Sync/Async, Active Serial |