EP20K400GI655-1 vs EP20K400GC655-1V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-1 sa pamamagitan ng Altera at EP20K400GC655-1V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GI655-1 | EP20K400GC655-1V |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KE |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | — |
| Logic Elements | 16640 | 16,640 |
| Typical Gates | 400000 | — |
| Maximum User I/O | 502 | 496 |
| Dedicated Inputs | 4 | 6 |
| Total Terminals | 655 | 655 |
| Propagation Delay | 2.5 ns | 2.5 ns |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | — |
| JESD-30 Package Code | S-CPGA-P655 | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Moisture Sensitivity Level | MSL 1 | MSL 1 |
| Peak Reflow Temperature | 220 C | 220 °C |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| Tindminan RoHS | Compliant | — |
| Typical Gate Count | — | 400,000 gates |
| Embedded Memory | — | 212,992 bits |
| Packhaging | — | CBGA-655 (Ceramic Ball Grid Array) |
| Supply Voltage (Core) | — | 2.375 V to 2.625 V (nominal 2.5 V) |
| Maximum Internal Frequency | — | 250 MHz (-1V speed grade) |
| Process Technology | — | 0.22 µm CMOS |
| LVDS Support | — | Yes |
| Qualification | — | Not Qualified |
| Programming Interface | — | IEEE 1532 / JTAG |