EP20K400GI655-1 vs EP20K400GI655-2V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-1 sa pamamagitan ng Altera at EP20K400GI655-2V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400GI655-1 | EP20K400GI655-2V |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | — |
| Technology | CMOS, SRAM-based | — |
| Logic Elements | 16640 | 16,640 |
| Typical Gates | 400000 | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 4 | 6 |
| Total Terminals | 655 | — |
| Propagation Delay | 2.5 ns | 3.0 ns to 3.1 ns |
| Package Type | Ceramic Pin Grid Array (CPGA-655) | — |
| JESD-30 Package Code | S-CPGA-P655 | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | Industrial (per -2V speed grade) |
| Moisture Sensitivity Level | MSL 1 | — |
| Peak Reflow Temperature | 220 C | — |
| Programmability | In-system, JTAG boundary-scan (IEEE 1149.1) | — |
| Process Node | 0.18 micrometer CMOS | — |
| Tindminan RoHS | Compliant | Non-compliant (ceramic SPGA, contains lead) |
| Maximum Gates | — | 400,000 |
| Embedded RAM Bits | — | 212,992 |
| User I/O Pins | — | 496 |
| Packhaging | — | SPGA-655 (ceramic, 47 x 47 mm) |
| Package Equivalence Code | — | SPGA655,47X47 |
| Process Technology | — | 0.18 µm CMOS |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | 3.3 V |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 1 |
| Package Body Material | — | Ceramic |