EP20K400GI655-2 vs EP20K400GI655-1V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-2 sa pamamagitan ng Altera at EP20K400GI655-1V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K400GI655-1V - APEX 20K 400K Gate FPGA, 655-pin CBGA | Intel
EP20K400GI655-1V ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K400GI655-2 | EP20K400GI655-1V |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Manufacturer | Altera Corporation | — |
| Series | APEX 20K (EP20K400) | — |
| Device Type | Field Programmable Gate Array (FPGA) | — |
| Typical Gate Count | 400,000 gates | — |
| Logic Elements (LE) | 16,640 | — |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Number of Terminals | 655 | — |
| Packhaging | SPGA-655 (47 mm x 47 mm) | — |
| Nominal Supply Voltage | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Propagation Delay | 3.1 ns (typical) | 2.5 ns |
| Technology | CMOS SRAM | — |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: industrial vs military grade] |
| Uri ng Pagpapasok | Through-Hole / Socket | — |
| Moisture Sensitivity Level | 1 (per Altera family) | — |
| Configuration Method | JTAG, Passive Serial, Passive Parallel | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+ | — |
| Embedded Memory | Embedded System Blocks (ESBs) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED] |
| Katayuan ng Lifecycle | Obsolete (legacy Altera APEX 20K family) | — |
| Family | — | APEX 20K |
| Typical Gates | — | 400,000 |
| Logic Elements | — | 16,640 |
| Package Type | — | CBGA-655 (Ceramic Ball Grid Array) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Package Equivalence Code | — | SPGA655, 47x47 |
| Process Technology | — | CMOS |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V / 3.3 V |
| Configuration | — | In-system programmable via JTAG |
| Boundary Scan | — | IEEE 1149.1 JTAG |
| Level ng MSL | — | 1 |
| Package Body Material | — | Ceramic |