EP20K400GI655-2V vs EP20K400GI655-1X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-2V sa pamamagitan ng Intel at EP20K400GI655-1X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400GI655-2V | EP20K400GI655-1X |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K |
| Maximum Gates | 400,000 | — |
| Logic Elements | 16,640 | 16640 |
| Embedded RAM Bits | 212,992 | — |
| User I/O Pins | 496 | — |
| Dedicated Inputs | 6 | 4 |
| Packhaging | SPGA-655 (ceramic, 47 x 47 mm) | — |
| Package Equivalence Code | SPGA655,47X47 | SPGA655,47X47 |
| Process Technology | 0.18 µm CMOS | CMOS, SRAM-based configuration |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | 3.3 V | — |
| Propagation Delay | 3.0 ns to 3.1 ns | 2.5 ns (typical for -1 grade) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 1 | 1 |
| Package Body Material | Ceramic | CERAMIC (metal-sealed co-fired) |
| Temperature na Operasyon | Industrial (per -2V speed grade) | -40 C to +85 C (industrial) |
| Tindminan RoHS | Non-compliant (ceramic SPGA, contains lead) | Compliant |
| Device | — | EP20K400 |
| Number of Terminals | — | 655 |
| User I/O Lines | — | 502 |
| Package Type | — | Ceramic Pin Grid Array (CPGA) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Speed Grade | — | -1 |
| Peak Reflow Temperature | — | 220 C |
| Uri ng Pagpapasok | — | Through-Hole (PGA) |