EP20K400GI655-2V vs EP20K400GI655-3V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-2V sa pamamagitan ng Intel at EP20K400GI655-3V sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K400GI655-3V - APEX 20K 400K-Gate FPGA, 16K LE, 655-Pin PGA | Altera (Intel)
EP20K400GI655-3V ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400GI655-2V | EP20K400GI655-3V |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | — |
| Maximum Gates | 400,000 | — |
| Logic Elements | 16,640 | 16,640 |
| Embedded RAM Bits | 212,992 | — |
| User I/O Pins | 496 | — |
| Dedicated Inputs | 6 | 6 |
| Packhaging | SPGA-655 (ceramic, 47 x 47 mm) | 655-pin SPGA (Staggered PGA), 47 x 47 mm |
| Package Equivalence Code | SPGA655,47X47 | — |
| Process Technology | 0.18 µm CMOS | — |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | 3.3 V | — |
| Propagation Delay | 3.0 ns to 3.1 ns | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 1 | 1 |
| Package Body Material | Ceramic | — |
| Temperature na Operasyon | Industrial (per -2V speed grade) | -40 °C to +85 °C (industrial) |
| Tindminan RoHS | Non-compliant (ceramic SPGA, contains lead) | [DATA_NEEDED: RoHS status] |
| Series | — | APEX 20K |
| Device Family | — | EP20K400 |
| Typical Gate Count | — | 400,000 gates |
| Maximum User I/O | — | 496 |
| Embedded System Blocks (ESBs) | — | [DATA_NEEDED: ESB count] |
| Total Embedded RAM | — | [DATA_NEEDED: total RAM bits] |
| Technology | — | CMOS (0.18 µm process) |
| Maximum Internal Clock Frequency | — | 714.2 MHz |
| Supply Voltage VCCINT | — | 2.5 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V |
| Uri ng Pagpapasok | — | Through-Hole (Pin Grid Array) |
| Qualification | — | Not Qualified |
| Configuration Interface | — | IEEE 1149.1 JTAG + serial / parallel passive |