EP20K600CB652C-8 vs EP20K600CB652C9N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C-8 sa pamamagitan ng Altera at EP20K600CB652C9N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CB652C-8 EP20K600CB652C9N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series APEX 20KC —
Family APEX 20KC (MultiCore) APEX 20KC
Typical Gates 600,000 600,000
Logic Elements 24,320 24,320
Embedded RAM 311,296 bits —
User I/Os 488 —
Propagation Delay 1.48 ns (per published source) —
Packhaging 652-BGA (LBGA, 45 x 45 mm, 1.27 mm pitch) BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch)
Uri ng Pagpapasok Surface Mount (thermally enhanced) Surface Mount (BGA)
Temperature na Operasyon 0 C to 85 C (commercial) 0 C to 85 C (commercial)
Speed Grade -8 (slowest, most timing margin) C9 (~1.48 ns propagation delay)
VCCIO Options 1.8 V / 2.5 V / 3.3 V —
Process 0.15 µm all-layer copper metal —
PCI Compliance PCI Local Bus Rev 2.2 at 33/66 MHz, 32/64-bit —
Memory Interface Support DDR SDRAM, ZBT SRAM, QDR SRAM, LVDS —
Configuration Enhanced (EPC) bitstream —
Device Type — Loadable PLD (FPGA)
Maximum User I/O — 488
Process Technology — 0.15 micron all-layer copper CMOS
Core Supply Voltage — 1.8 V
Architecture — MultiCore LUT + embedded system memory (ESB)
On-chip Memory — Embedded system memory blocks (dual-port RAM, FIFO)
Configuration Interface — JTAG (IEEE 1149.1) and serial/PROM configuration
Pin/Pin Compatibility — Pin-compatible with APEX 20KE devices of same package
Toolchain — Altera/Intel Quartus II (legacy APEX support)
Tindminan RoHS — [DATA_NEEDED: rohs status]
Level ng MSL — [DATA_NEEDED: MSL level]

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