EP20K600CB652C7ES vs EP20K600CB652C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C7ES sa pamamagitan ng Altera at EP20K600CB652C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB652C7ES | EP20K600CB652C7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| System Gates | 600,000 | 600,000 |
| Maximum System Gates | 1,053,840 | — |
| Embedded Memory Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 26 | — |
| Maximum User I/O | 488 | — |
| User I/O (this package) | 488 (652-BGA) | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Internal Clock Frequency | 1666.6 MHz | — |
| Propagation Delay | 1.6 ns | 1.48 ns |
| Process Technology | 0.15 µm CMOS | 0.15 um all-layer copper-metal |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0 C to 85 C |
| Package Type | 652-ball FineLine BGA | — |
| JEDEC Package Code | S-PBGA-B652 | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| PLLs | 4 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Device Type | — | SPLD / Loadable PLD (FPGA) |
| Embedded Memory (bits) | — | 311,296 |
| Maximum User I/Os | — | 488 |
| Internal Operating Frequency | — | 375.94 MHz |
| Core Supply Voltage | — | 1.8 V |
| Packhaging | — | 652-ball BGA (PBGA-652, S-PBGA-B652) |
| Package Dimensions | — | 45 x 45 mm |
| Ball Pitch | — | 1.27 mm |