EP20K600CB652C9N vs EP20K600EBI652-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB652C9N sa pamamagitan ng Intel at EP20K600EBI652-2X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K600EBI652-2X - 600K Gate APEX 20KE FPGA 488 I/O BGA-652 | Intel
EP20K600EBI652-2X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K600CB652C9N | EP20K600EBI652-2X |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KE |
| Device Type | Loadable PLD (FPGA) | — |
| Typical Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 cells |
| Maximum User I/O | 488 | — |
| Packhaging | BGA-652 (652-ball FineLine BGA, 45 x 45 mm, 1.27 mm pitch) | 652-ball BGA (45 x 45 mm, 1.27 mm pitch, thermally enhanced) |
| Process Technology | 0.15 micron all-layer copper CMOS | 0.18 µm all-layer copper CMOS |
| Core Supply Voltage | 1.8 V | — |
| Speed Grade | C9 (~1.48 ns propagation delay) | -2X (mid-tier) |
| Architecture | MultiCore LUT + embedded system memory (ESB) | — |
| On-chip Memory | Embedded system memory blocks (dual-port RAM, FIFO) | — |
| Configuration Interface | JTAG (IEEE 1149.1) and serial/PROM configuration | — |
| Temperature na Operasyon | 0 C to 85 C (commercial) | 0 C to 85 C (commercial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Pin/Pin Compatibility | Pin-compatible with APEX 20KE devices of same package | — |
| Toolchain | Altera/Intel Quartus II (legacy APEX support) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Lead-free / RoHS compliant |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Maximum Gates | — | 600,000 gates |
| User I/Os | — | 488 |
| Embedded RAM | — | 311 Kbits |
| Dedicated Inputs | — | 4 |
| Maximum Operating Frequency | — | 200 MHz |
| Propagation Delay | — | 1.48 ns |
| Core Voltage | — | 1.8 V |
| PLLs | — | 4 |
| MultiVolt I/O Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Configuration Method | — | Serial/parallel EPROM, JTAG, controller |