EP20K600CB672C7 vs EP20K600CEF672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB672C7 sa pamamagitan ng Altera at EP20K600CEF672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB672C7 | EP20K600CEF672C7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC (Enhanced Configuration) |
| Device Type | FPGA / Programmable Logic Device (PLD) | FPGA / Loadable PLD |
| Typical Gates | 600,000 | — |
| Maximum System Gates | 1,053,840 | — |
| Logic Elements | 30,960 (typical) | — |
| Embedded Memory | 311 kbits (EAB-based) | EAB blocks (dual-port RAM with byte enables) |
| User I/Os | 488 | 488 |
| Packhaging | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) | 672-ball FineLine BGA (FC-FBGA) |
| Speed Grade | C7 (commercial, 0 °C to 85 °C) | — |
| Propagation Delay | 1.48 ns | 1.48 ns (typ) |
| Process Technology | 0.15 µm all-layer copper-metal CMOS | 0.15 µm CMOS, all-layer copper |
| Core Voltage | 2.5 V | — |
| I/O Voltage Support | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) | — |
| Number of PLLs | 4 | — |
| Dual-Port RAM | Yes (4.5 ns access) | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Configuration Method | EPC configuration devices / JTAG / passive serial | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | APEX 20KC |
| Logic Elements / Cells | — | 24,320 |
| Gate Count (typical) | — | 600,000 gates |
| Maximum Operating Frequency | — | 375.94 MHz |
| Core Supply Voltage | — | 1.8 V |
| Package Code | — | BGA-652, 45 x 45 mm, 1.27 mm pitch |
| Configuration | — | SRAM-based, serial or parallel (EPC) |
| LVDS Support | — | True-LVDS channels integrated |
| MultiVolt I/O | — | 1.8 V, 2.5 V, 3.3 V interfaces |
| External Memory Interface | — | DDR SDRAM, QDR SRAM |
| JTAG Support | — | IEEE 1149.1 boundary-scan |