EP20K600CB672C7 vs EP20K600CF1020C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CB672C7 sa pamamagitan ng Altera at EP20K600CF1020C8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CB672C7 | EP20K600CF1020C8 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Device Type | FPGA / Programmable Logic Device (PLD) | — |
| Typical Gates | 600,000 | — |
| Maximum System Gates | 1,053,840 | — |
| Logic Elements | 30,960 (typical) | — |
| Embedded Memory | 311 kbits (EAB-based) | — |
| User I/Os | 488 | — |
| Packhaging | 672-ball FineLine BGA (45 x 45 mm, 1.27 mm pitch) | 1020-ball FC-FBGA (1.00 mm pitch) |
| Speed Grade | C7 (commercial, 0 °C to 85 °C) | C8 |
| Propagation Delay | 1.48 ns | — |
| Process Technology | 0.15 µm all-layer copper-metal CMOS | 0.15 µm CMOS |
| Core Voltage | 2.5 V | — |
| I/O Voltage Support | 1.8 V, 2.5 V, 3.3 V (MultiVolt I/O) | — |
| Number of PLLs | 4 | — |
| Dual-Port RAM | Yes (4.5 ns access) | — |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, AGP, HSTL, CTT | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial, "C") |
| Configuration Method | EPC configuration devices / JTAG / passive serial | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Series | — | EP20K600 |
| Logic Elements / Cells | — | 24,320 |
| System Gates | — | 600,000 |
| Embedded Memory (ESB) | — | 311 Kbit (max) |
| Core Supply Voltage | — | 1.8 V |
| I/O Supply Voltage | — | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Maximum Internal Frequency | — | 301.21 MHz (C8 speed grade) |
| User I/O Pins | — | 588 |
| Dedicated Inputs | — | 4 |
| Configuration Interface | — | Serial / JTAG (IEEE 1149.1) |
| PCI Compliance | — | PCI SIG Local Bus Spec Rev 2.2, 32/64-bit, 33/66 MHz, 3.3 V |