EP20K600CF672C-7ES vs EP20K600CF672C7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C-7ES sa pamamagitan ng Altera at EP20K600CF672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C-7ES EP20K600CF672C7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX 20KC —
Device Type Field Programmable Gate Array (FPGA) —
Maximum System Gates 1,560,000 (typical 600K application gates) 1,052,000
Typical Logic Elements 24,320 (per APEX 20KC 600K family) —
Maximum User I/O 488 —
Total I/O Lines 504 (per Microchip USA listing) —
Total Inputs 508 —
Embedded System Blocks (ESBs) 248 —
Embedded RAM 248 Kbits (dual-port) —
PLLs 4 —
Propagation Delay 1.48 ns to 1.6 ns 1.48 ns
Maksimum na Taktiko ng Oras 1666.6 MHz —
Speed Grade -7 C7
Process Technology 0.15 micron all-layer copper CMOS 0.15 µm all-layer copper-metal CMOS
Packhaging 672-ball FCBGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch
Temperature na Operasyon 0 C to 85 C (Commercial) 0 °C to +85 °C (Commercial)
Core Voltage 1.8 V (typical APEX 20KC, exact value per datasheet) 1.8 V
Configuration Mode EPC serial / JTAG IEEE 1149.1 —
Compliance RoHS status unknown (verify with manufacturer datasheet) —
Device Family — APEX 20KC
Typical Gates — 600,000
Logic Elements / Cells — 24,320
Maximum User I/O Pins — 488
Total Package Pins — 652
Maximum Operating Frequency — 375.94 MHz
Architecture — MultiCore (LUT + Embedded System Memory)
Seated Height — 3.50 mm
Uri ng Pagpapasok — Surface Mount (BGA)
Tindminan RoHS — unknown

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