EP20K600CF672C-8 vs EP20K600CF672C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C-8 sa pamamagitan ng Altera at EP20K600CF672C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K600CF672C-8 - APEX 20KC FPGA 600K Gates 24320 LEs 672-BGA | Intel / Altera
EP20K600CF672C-8 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K600CF672C-8 | EP20K600CF672C8 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Unknown |
| Series | APEX 20KC | — |
| Device Type | FPGA (Field Programmable Gate Array) | Field Programmable Gate Array (FPGA) |
| Typical Gates | 600,000 | — |
| Logic Elements (LEs) | 24,320 | — |
| Embedded Memory Bits | 311,296 | — |
| Maximum User I/Os | 508 | — |
| Bilang ng Pins | 672 | — |
| Package Type | 672-BGA (FineLine BGA, 1.27 mm pitch, 45 x 45 mm) | FBGA |
| Speed Grade | -8 | — |
| Propagation Delay (tPD) | 1.48 ns | — |
| Process Technology | 0.15 micrometer all-layer copper-metal | — |
| Architecture | MultiCore (LUT logic + embedded memory) | — |
| Hanay ng Temperature na Operasyon | 0C to +85C (commercial) | — |
| Volte ng Pagbibigay | Multi-rail (core + I/O banks) | 1.71 V to 1.89 V |
| Configuration Method | Serial / parallel / JTAG | — |
| Pin Compatibility | Pin-compatible with APEX 20KE family | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant |
| Product Family | — | APEX-20K |
| User I/O Count | — | 508 |
| Logic Elements | — | 24,320 |
| Total RAM Bits | — | 311,296 bits |
| Propagation Delay | — | 1.48 ns |
| Package Pin Count | — | 672 balls |
| Supplier Device Package | — | 672-FBGA, 27 mm x 27 mm |
| Alternate Package Description | — | BGA-652, 45 mm x 45 mm, 1.27 mm pitch |
| Uri ng Pagpapasok | — | Surface Mount |
| Temperature na Operasyon | — | 0 C to 85 C |
| Fabrication Process | — | 0.15 um |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| Configuration Interface | — | [DATA_NEEDED: configuration interface] |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency] |