EP20K600CF672C7N vs EP20K600CF672C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7N sa pamamagitan ng Altera at EP20K600CF672C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CF672C7N | EP20K600CF672C6 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | APEX 20KC | — |
| Maximum System Gates | 1,052,000 | — |
| Typical Gates | 600,000 | — |
| Logic Elements / Cells | 24,320 | — |
| Maximum User I/O Pins | 488 | 508 |
| Total Package Pins | 652 | — |
| Packhaging | FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA (CF672) |
| Core Voltage | 1.8 V | 1.8 V |
| Maximum Operating Frequency | 375.94 MHz | — |
| Propagation Delay | 1.48 ns | — |
| Process Technology | 0.15 µm all-layer copper-metal CMOS | 0.18 µm CMOS, 6 metal layers |
| Architecture | MultiCore (LUT + Embedded System Memory) | — |
| Temperature na Operasyon | 0 °C to +85 °C (Commercial) | 0 °C to +85 °C (commercial) |
| Speed Grade | C7 | -6 (C6) |
| Seated Height | 3.50 mm | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Tindminan RoHS | unknown | Non-RoHS (legacy process) |
| Family | — | APEX 20KC |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Embedded System Blocks (ESBs) | — | 160 (each 2,048 bits) |
| Maximum Embedded RAM | — | 311,296 bits (311 kbit) |
| Package Body Size | — | 27 mm × 27 mm |
| I/O Standards Supported | — | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | — | 4 |
| Configuration Method | — | SRAM-based, JTAG, EPC16/EPC2 |