EP20K600CF672C7N vs EP20K600CF672I8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672C7N sa pamamagitan ng Altera at EP20K600CF672I8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K600CF672C7N EP20K600CF672I8
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family APEX 20KC —
Maximum System Gates 1,052,000 —
Typical Gates 600,000 —
Logic Elements / Cells 24,320 24,320
Maximum User I/O Pins 488 —
Total Package Pins 652 —
Packhaging FC-FBGA (BGA-652) 45 x 45 mm, 1.27 mm pitch —
Core Voltage 1.8 V —
Maximum Operating Frequency 375.94 MHz —
Propagation Delay 1.48 ns —
Process Technology 0.15 µm all-layer copper-metal CMOS 0.15 µm all-layer copper
Architecture MultiCore (LUT + Embedded System Memory) —
Temperature na Operasyon 0 °C to +85 °C (Commercial) 0 °C to +85 °C (Industrial)
Speed Grade C7 —
Seated Height 3.50 mm —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Tindminan RoHS unknown Compliant per legacy product records
Family — APEX 20KC
Device Type — SPLD / FPGA
Macros (Logic Cells) — 2432
Typical Gate Count — 600,000 gates
Embedded Memory — 311,296 bits
User I/Os — 488 to 508
Bilang ng Pins — 652 (functional) / 672 (BGA balls)
Propagation Delay (typical) — 1.48 ns
Internal Frequency (max) — [DATA_NEEDED: max internal frequency in MHz]
Core Supply Voltage — 1.8 V
Package Type — 672-ball BGA, 45 x 45 mm, 1.27 mm pitch
Configuration Interface — JTAG / Passive Serial
Design Tool — Quartus II (legacy MAX+PLUS II)

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