EP20K600CF672I7N vs EP20K600CF672I9N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600CF672I7N sa pamamagitan ng Intel at EP20K600CF672I9N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600CF672I7N | EP20K600CF672I9N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX 20KC | APEX 20KC |
| Technology | 0.15 µm CMOS | — |
| Maximum System Gates | 600,000 | — |
| Logic Elements | 24,320 | 24,320 cells |
| Maximum User I/O Pins | 508 | — |
| Maximum Internal Frequency | 376 MHz | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Total Embedded RAM (max) | 311,296 bits | — |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V (MultiVolt, bank-dependent) | [DATA_NEEDED: VCCIO range] |
| Packhaging | 672-ball FineLine BGA (FC-FBGA) | 672-ball FC-FBGA |
| Ball Pitch | 1.0 mm | — |
| Package Body Size | 27 mm × 27 mm | — |
| Speed Grade | I7 (-40 °C to +100 °C industrial) | — |
| Propagation Delay (typical) | 1.6 ns | — |
| Configuration Method | JTAG (IEEE 1149.1) + EPC configuration device | — |
| Lead-Free Finish (N suffix) | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Typical Gates | — | 600,000 |
| Maximum Frequency | — | 250 MHz |
| Process Technology | — | 0.15 µm CMOS |
| Embedded Memory | — | 311,040 bits (approx. 38 KB) |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| User I/O Pins | — | [DATA_NEEDED: max user I/O] |
| Configuration Mode | — | JTAG / Serial / Parallel |
| Programming Interface | — | IEEE 1149.1 JTAG |
| Temperature na Operasyon | — | -40 °C to +85 °C (industrial) |