EP20K600EBC652-3 vs EP20K600EBC652-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600EBC652-3 sa pamamagitan ng Intel at EP20K600EBC652-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600EBC652-3 | EP20K600EBC652-2X |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KE | — |
| Family | APEX 20K | — |
| Device Type | FPGA (Field Programmable Gate Array) / SPLD Loadable | SPLD / FPGA (Field Programmable Gate Array) |
| Logic Elements | 24320 | — |
| Embedded Memory | 311296 bits | — |
| User I/Os | 488 | 488 |
| Number of Terminals | 652 | — |
| Package Type | BGA-652 (45 x 45 mm, 1.27 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Propagation Delay | 1.48 ns | 1.48 ns |
| Temperature na Operasyon | 0 C to 85 C | 0 °C to +85 °C (commercial) |
| Speed Grade | -3 | — |
| Process Technology | 0.15-micron all-layer copper CMOS | 0.15 µm all-layer copper CMOS |
| Core Voltage | [DATA_NEEDED: core voltage] | — |
| I/O Voltage Support | Multi-volt 3.3 V / 2.5 V / 1.8 V | — |
| Configuration Method | JTAG / serial / passive parallel | — |
| PLLs | 4 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Device Family | — | APEX 20KE |
| Logic Elements (LEs) | — | 24,320 |
| Macros | — | 24,320 |
| Embedded Memory Bits | — | 311,296 bits |
| Packhaging | — | 652-ball BGA, 45 x 45 mm, 1.27 mm pitch |
| Total Pins / Balls | — | 652 |
| Core Supply Voltage | — | 2.5 V |
| I/O Standard Support | — | LVTTL, LVCMOS, PCI, SSTL, GTL+ |
| Configuration Modes | — | Passive serial, passive parallel, JTAG (IEEE 1149.1) |