EP20K600EBC652-3 vs EP2A40B652C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K600EBC652-3 sa pamamagitan ng Intel at EP2A40B652C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K600EBC652-3 | EP2A40B652C8 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Series | APEX-20KE | — |
| Family | APEX 20K | APEX 20A |
| Device Type | FPGA (Field Programmable Gate Array) / SPLD Loadable | — |
| Logic Elements | 24320 | 40,960 |
| Embedded Memory | 311296 bits | — |
| User I/Os | 488 | — |
| Number of Terminals | 652 | — |
| Package Type | BGA-652 (45 x 45 mm, 1.27 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Propagation Delay | 1.48 ns | — |
| Temperature na Operasyon | 0 C to 85 C | 0C to +85C (Commercial, C8 suffix) |
| Speed Grade | -3 | C8 |
| Process Technology | 0.15-micron all-layer copper CMOS | 0.18 micrometer CMOS SRAM |
| Core Voltage | [DATA_NEEDED: core voltage] | 1.8 V |
| I/O Voltage Support | Multi-volt 3.3 V / 2.5 V / 1.8 V | — |
| Configuration Method | JTAG / serial / passive parallel | Serial (PS) or Passive Parallel Async (PPA), JTAG |
| PLLs | 4 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free] | — |
| Device | — | EP2A40 |
| Maximum User I/O | — | 718 |
| Embedded Memory (bits) | — | 425,984 |
| Embedded System Blocks | — | Configurable as dual-port RAM or CAM |
| I/O Voltage | — | 3.3 V (LVTTL/LVCMOS) |
| Packhaging | — | 652-ball FineLine BGA |