EP2A25F672I7N vs EP2A25F672ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672I7N sa pamamagitan ng Intel at EP2A25F672ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A25F672I7N | EP2A25F672ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements (Cells) | 24,320 | — |
| Typical Gate Count | 900,000 | — |
| Maximum Internal Frequency | 500 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS |
| Core Supply Voltage | 1.5 V | — |
| Packhaging | 672-ball FC-FBGA | 672-ball FC-FBGA |
| Pin/Ball Count | 672 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Operating Temperature Grade | Industrial (I) | — |
| Speed Grade | 7 | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel | — |
| Design Software | Quartus II | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Katayuan ng Lifecycle | Not Recommended for New Designs (NRND) | — |
| Logic Elements | — | 24,320 |
| Maximum Gates | — | 900,000 |
| Embedded System Blocks (ESBs) | — | 24 |
| Maximum Embedded RAM | — | 1.4 Mbit |
| Maximum User I/O Pins | — | 492 |
| Core Voltage | — | 1.5 V |
| Maximum System Clock Frequency | — | 500 MHz |
| Number of PLLs | — | 4 |
| I/O Banks | — | 16 |
| Supported I/O Standards | — | LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL |
| Configuration Mode | — | Serial / Parallel / JTAG |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |