EP2A25F672I8N vs EP2A25F672I9N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672I8N sa pamamagitan ng Intel at EP2A25F672I9N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2A25F672I8N - APEX II FPGA 900K Gates 672-BGA | Intel / Altera
EP2A25F672I8N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2A25F672I8N | EP2A25F672I9N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | APEX II | APEX II |
| Device | EP2A25 | — |
| Logic Elements | 24,320 | — |
| Gates | 900,000 | — |
| Embedded Memory (bits) | 622,592 | — |
| User I/Os | 492 | — |
| Packhaging | 672-ball FC-FBGA (FineLine BGA) | 672-pin FC-FBGA |
| Package Size | 27 x 27 mm | — |
| Ball Pitch | 1 mm | — |
| Process Technology | 0.15 µm all-layer copper-metal | 0.15 µm CMOS |
| Metal Layers | Up to 8 | — |
| Core Voltage (VCCINT) | 1.5 V | — |
| Internal Frequency (max) | 333 MHz | — |
| Propagation Delay | 1.69 ns | — |
| Temperature na Operasyon | 0 °C to 85 °C | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Logic Family | CMOS | — |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | — |
| Configuration Method | SRAM-based (Altera Quartus II) | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: confirmed] |
| Lead-Free | unknown | — |
| Series | — | APEX II (EP2A25) |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Logic Elements / Cells | — | 24,320 |
| System Gates | — | 900,000 (typical) |
| Maximum Internal Frequency | — | 236 MHz |
| Propagation Delay (tpd) | — | 2.23 ns |
| Core Supply Voltage (VCCINT) | — | 1.5 V nominal (1.425 V to 1.525 V) |
| I/O Supply Voltage | — | [DATA_NEEDED: VCCIO range] |
| Uri ng Pagpapasok | — | Surface Mount |
| Speed Grade | — | 9 (fastest commercial APEX II) |
| Embedded System Blocks (ESB) | — | Yes (on-chip RAM/ROM) |
| PLLs | — | 4 |
| Configuration | — | JTAG / in-system programmable |
| Level ng MSL | — | [DATA_NEEDED] |
| AEC-Q100 | — | not_applicable |