EP2A40F1020C8N vs EP2A40F1020C9ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F1020C8N sa pamamagitan ng Intel at EP2A40F1020C9ES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2A40F1020C9ES - APEX II FPGA 1.5M Gates 38400 Cells 366MHz | Altera
EP2A40F1020C9ES ObsoletePagsanggunian na paghahambing
| Parametro | EP2A40F1020C8N | EP2A40F1020C9ES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | — |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | Flip-Chip Fine-Pitch Ball Grid Array |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| Temperature na Operasyon | 0 °C to 85 °C | [DATA_NEEDED: operating temperature grade] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Terminal Form | Ball | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II |
| System Gates | — | 1.5 M |
| Logic Cells / Elements | — | 38,400 |
| Maximum Internal Clock Frequency | — | 366 MHz |
| Process Technology | — | 0.15 µm CMOS |
| Core Supply Voltage | — | 1.5 V |
| Packhaging | — | 1020-pin FC-FBGA |
| Embedded Memory | — | Embedded System Blocks (ESBs) - RAM/ROM |
| I/O Standards | — | LVDS and other high-speed standards (per family datasheet) |
| RAM Support | — | Synchronous and asynchronous |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |