EP2A40F1020C8N vs EP2A40F1020I8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F1020C8N sa pamamagitan ng Intel at EP2A40F1020I8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F1020C8N | EP2A40F1020I8 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Field-Programmable Gate Array (FPGA) | — |
| Device Family | APEX II | — |
| Logic Technology | CMOS | — |
| Logic Gates | 1.5 million | — |
| Logic Cells | 38,400 | — |
| Nominal Supply Voltage | 1.5 V | — |
| Supply Voltage Range | 1.425 V to 1.575 V | — |
| User I/Os | 735 | — |
| Package Terminal Count | 1,020 pins | — |
| Package Type | FC-FBGA, BGA-1020 | — |
| Package Body Size | 33 mm x 33 mm | — |
| Ball Pitch | 1 mm | — |
| Reported Operating Frequency | 376 MHz | — |
| Alternative Reported Frequency | 562 MHz | — |
| Reported Propagation Delay | 1.78 ns | — |
| Alternative Reported Propagation Delay | 1.55 ns | — |
| Fabrication Process | 0.15 µm | — |
| Maximum Reported Metal Layers | 8 layers | — |
| Temperature na Operasyon | 0 °C to 85 °C | -40C to +85C (Industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Terminal Form | Ball | — |
| Tindminan RoHS | unknown | Depends on lot - check manufacturer declaration |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Family | — | APEX II |
| Logic Elements | — | 2,560 (40,000 max with embedded array blocks) |
| Typical Gates | — | 38,400 |
| System Gates | — | 655,360 |
| User I/O Pins | — | 735 |
| Packhaging | — | 1020-ball FineLine BGA (FBGA) |
| Process Technology | — | 0.18 micron CMOS |
| Embedded RAM Bits | — | 409,600 (via EABs) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core voltage] |
| Supply Voltage (I/O) | — | [DATA_NEEDED: I/O voltage] |
| I/O Banks | — | 8 |
| PLLs | — | [DATA_NEEDED: PLL count] |
| Configuration Modes | — | JTAG, Passive Serial, Passive Parallel, Synchronous |
| In-System Programmability | — | Yes |