EP2A40F1020I9N vs EP2A40F1020I8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F1020I9N sa pamamagitan ng Intel at EP2A40F1020I8N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F1020I9N | EP2A40F1020I8N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II (EP2A40) |
| Device Logic Elements / Cells | 38,400 cells | — |
| System Gates | 1,500,000 (1.5 M) | 1.5 M (typical) |
| Maximum Operating Frequency | 366 MHz | — |
| Process Technology | 0.15 um CMOS, up to 8 metal layers | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | — |
| User I/O Count | 735 bidirectional I/O | 735 (maximum) |
| Packhaging | 1020-pin FC-FBGA (Flip-Chip FineLine BGA) | 1020-pin FC-FBGA (Flip-Chip Fine-pitch BGA) |
| Operating Temperature Grade | Industrial (I9 suffix: -40C to +100C per Altera APEX II convention) | Industrial (-40 C to +100 C) / 'I' suffix |
| High-Speed I/O Standards | True-LVDS (up to 1 Gbps), LVPECL, PCML, HyperTransport | — |
| Embedded Memory | ESB-based True-Dual-Port/Single-Port RAM, ROM, CAM (bits [DATA_NEEDED: total RAM bits]) | — |
| Clock Management | PLLs (count [DATA_NEEDED: PLL count]) | — |
| Configuration Modes | Passive Serial, Passive Parallel Asynchronous/Synchronous, JTAG | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Katayuan ng Lifecycle | Obsolete (per distributor listings / Altera APEX II family EOL) | — |
| Logic Elements | — | 38,400 cells |
| Core Voltage | — | 1.5 V |
| Maximum Internal Frequency | — | 376 MHz |
| Speed Grade | — | 8 |
| Architecture | — | LUT-based with embedded system blocks (ESBs) |
| Configuration | — | SRAM-based, JTAG / passive serial / passive parallel |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Number of PLLs | — | [DATA_NEEDED: PLL count] |
| Total Embedded Memory | — | [DATA_NEEDED: embedded memory bits] |