EP2A40F672C6 vs EP2A40F672C8 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C6 sa pamamagitan ng Altera at EP2A40F672C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672C6 EP2A40F672C8
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family APEX II APEX II
Device EP2A40 —
Logic Elements (typical) 40,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates] —
Embedded System Blocks (ESBs) [DATA_NEEDED: ESB count] —
Maximum User I/O Pins [DATA_NEEDED: max user I/O count] —
Packhaging 672-ball FineLine BGA (FBGA-672) —
Speed Grade C6 (commercial) —
Temperature na Operasyon Commercial (0C to +85C) 0 C to 85 C (commercial)
Process Technology 0.18-micron CMOS 0.15-micron all-layer copper, up to 8 metal layers
Configuration Memory SRAM-based —
JTAG Support Yes (IEEE 1149.1) —
PLL Support Yes —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Lead-Free [DATA_NEEDED: lead-free status] —
Lifecycle Obsolete / EOL (per Intel/Altera product discontinuation notice) —
Logic Family — CMOS
Typical Logic Elements (LEs) — 40,000
Embedded Memory — Up to 1.5 Mbits
User I/Os — 492 pins
Bilang ng Pins — 672
Package Type — FineLine BGA, 27 x 27 mm, 1.0 mm pitch
Propagation Delay (speed grade C8) — 1.55 ns
Phase-Locked Loops (PLLs) — 4
LVDS Signaling Support — Up to 1 Gbps
Multipliers — Embedded multiplier blocks
I/O Standards — LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS

Mga Datasheets at Resources

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