EP2A40F672C6N vs EP2A40F1020I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C6N sa pamamagitan ng Intel at EP2A40F1020I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F672C6N | EP2A40F1020I7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | — |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| Packhaging | 672-ball FineLine BGA | 1020-pin FC-FBGA |
| Temperature na Operasyon | Commercial (0C to +85C) | -40C to +100C (Industrial) |
| Speed Grade | C6 (per part number suffix) | I7 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 µm |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Device Logic Elements | — | 38,400 cells |
| System Gates | — | 1,500,000 |
| Maximum Operating Frequency | — | 562 MHz |
| Architecture | — | PLA-type / Look-up Table hybrid |
| Number of PLLs | — | [DATA_NEEDED: PLL count] |
| Embedded Memory | — | [DATA_NEEDED: total embedded memory bits] |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Design Software | — | Quartus II |