EP2A40F672C7N vs EP2A40F672I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C7N sa pamamagitan ng Intel at EP2A40F672I7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F672C7N | EP2A40F672I7 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements / Cells | 38,400 | — |
| System Gates | 1.5 M | — |
| Maximum User I/Os | 492 | — |
| Propagation Delay (tpd) | 1.55 ns | — |
| Internal Performance | 562 MHz | — |
| Process Technology | 0.15 µm CMOS, all-layer copper, up to 8 metal layers | 0.15 µm CMOS |
| Core Voltage | 1.5 V | — |
| MultiVolt I/O Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5.0 V | — |
| Logic Family | CMOS | — |
| Packhaging | 672-ball FC-FBGA (FineLine BGA), S-PBGA-B672, 27 x 27 mm, 1.0 mm pitch | 672-ball FC-FBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 °C to 85 °C (commercial, 'C' grade) | -40 °C to +85 °C (Industrial) |
| Speed Grade | 7 | -7 (speed grade 7) |
| Lead-Free / RoHS | Yes (N suffix) | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| Logic Elements | — | 38,400 |
| Maximum System Gates | — | 1,500,000 |
| Maximum User I/O | — | [DATA_NEEDED: max user I/O pins for F672 package] |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO supported levels] |
| Core Frequency (max) | — | 562 MHz |
| Package Family | — | Fine-pitch Chip-scale BGA |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | 3 |
| Peak Reflow Temperature | — | 220 °C |
| Configuration Method | — | JTAG / Passive Serial / Active Serial |
| Tindminan RoHS | — | unknown |