EP2A40F672C9 vs EP2A40F672C7ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C9 sa pamamagitan ng Altera at EP2A40F672C7ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2A40F672C9 - APEX II FPGA 1.5M Gates 38400 Cells 672-BGA | Altera
EP2A40F672C9 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP2A40F672C9 | EP2A40F672C7ES |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | APEX II | APEX II |
| Device Family | APEX II PLD | — |
| Logic Elements / Cells | 38,400 | — |
| System Gates | 1.5 M | — |
| Macros | 2,560 | — |
| User I/Os | 492 | — |
| Bilang ng Pins | 672 | — |
| Packhaging | 672-BBGA, FC-FBGA (FineLine) | 672-pin FC-FBGA (FineLine BGA) |
| Package Size | 27 mm × 27 mm, 1 mm ball pitch | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm CMOS |
| Logic Family | CMOS | — |
| Propagation Delay | 1.55 ns | — |
| Internal Speed Grade | 366 MHz | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | 0 °C to +85 °C (commercial) |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Logic Elements | — | 38400 |
| Typical Gates | — | 1.5 M |
| Maximum Logic Elements | — | 40960 |
| Maximum Macro Cells | — | 2560 |
| Maximum User I/O | — | 492 |
| Maximum Operating Frequency | — | 562 MHz |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V |
| Package Dimensions | — | 27 × 27 mm |
| Ball Pitch | — | 1.0 mm |
| Speed Grade | — | 7 |
| Status Code | — | ES (Engineering Sample) |