EP2A40F672I-9 vs EP2A40F672C9 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672I-9 sa pamamagitan ng Intel at EP2A40F672C9 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672I-9 EP2A40F672C9
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family APEX II APEX II
Device EP2A40 —
Logic Elements 38,400 —
System Gates 1,500,000 1.5 M
Maximum Operating Frequency 366 MHz —
Process Technology 0.15 µm CMOS 0.15 µm all-layer copper, up to 8 metal layers
Core Voltage (VCCINT) 1.5 V —
I/O Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) —
Temperature na Operasyon -40 °C to +100 °C (Industrial) 0 °C to 85 °C (commercial)
Packhaging 672-pin FC-FBGA (Fine-pitch Ball Grid Array) 672-BBGA, FC-FBGA (FineLine)
Speed Grade -9 —
True-LVDS Channels Yes (dedicated) —
Embedded Memory Dual-port RAM, single-port RAM, ROM, CAM (via ESBs) —
Hot Socketing Supported —
Configuration Mode Passive serial, passive parallel synchronous, passive parallel asynchronous, JTAG —
Moisture Sensitivity Level MSL 3 —
Peak Reflow Temperature 220 °C —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — APEX II PLD
Logic Elements / Cells — 38,400
Macros — 2,560
User I/Os — 492
Bilang ng Pins — 672
Package Size — 27 mm × 27 mm, 1 mm ball pitch
Core Voltage — 1.5 V
Logic Family — CMOS
Propagation Delay — 1.55 ns
Internal Speed Grade — 366 MHz
I/O Standards Supported — True-LVDS, LVPECL, PCML, HyperTransport
Uri ng Pagpapasok — Surface Mount

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