EP2A40F672I7 vs EP2A40F672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672I7 sa pamamagitan ng Altera at EP2A40F672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F672I7 | EP2A40F672C7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 38,400 | 38,400 |
| Maximum System Gates | 1,500,000 | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O pins for F672 package] | 492 |
| Core Voltage (VCCINT) | 1.5 V | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO supported levels] | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS, all-layer copper, up to 8 metal layers |
| Core Frequency (max) | 562 MHz | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | — |
| Packhaging | 672-ball FC-FBGA | 672-ball FC-FBGA (FineLine BGA) |
| Package Family | Fine-pitch Chip-scale BGA | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Speed Grade | -7 (speed grade 7) | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 | — |
| Peak Reflow Temperature | 220 °C | — |
| Configuration Method | JTAG / Passive Serial / Active Serial | — |
| Tindminan RoHS | unknown | Compliant |
| System Gates | — | 1,500,000 |
| Macro Cells | — | 2,560 |
| Core Voltage | — | 1.5 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Pin-to-Pin Delay | — | 1.55 ns (C7 speed grade) |
| Maximum Internal Frequency | — | 562 MHz |
| High-Speed Interface | — | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport |
| PLLs | — | 4 |
| Package Dimensions | — | 27 x 27 mm, 1.0 mm pitch |
| Operating Temperature Grade | — | Commercial (per 'C' suffix in speed grade) |
| Lead-Free | — | Yes |