EP2A40F780 vs EP2A40F724 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F780 sa pamamagitan ng Altera at EP2A40F724 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A40F780 | EP2A40F724 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | APEX II | APEX II |
| Device | EP2A40 | — |
| Typical Gates | 1,500,000 | — |
| Logic Elements | 30,000 | 38400 |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Packhaging | 780-ball FineLine BGA (FBGA) | 724-ball FineLine BGA (F724) |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0C to +85C (commercial) |
| Configuration Memory | SRAM-based | — |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Process Technology | [DATA_NEEDED: process node] | 0.15 µm CMOS |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Programming File Format | .sof/.pof via Quartus II | — |
| Core Voltage | [DATA_NEEDED: VCCINT] | 1.5 V |
| I/O Voltage | [DATA_NEEDED: VCCIO range] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Series | — | EP2A |
| System Gates | — | 1,500,000 (typical) |
| Maximum User I/O | — | 498 |
| Embedded RAM Bits | — | 655360 |
| CAM Blocks | — | Yes |
| PLLs | — | 4 |
| Global Clock Networks | — | 16 |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Programming Interface | — | JTAG (IEEE 1149.1) / Altera ByteBlaster |