EP2A70B724C8N vs EP2A70B724I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A70B724C8N sa pamamagitan ng Altera at EP2A70B724I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2A70B724C8N - APEX II FPGA, 3M Gates, 724-FCBGA | Altera / Intel
EP2A70B724C8N ⚠ Huling PagbiliIntel
EP2A70B724I7 - APEX II FPGA 3M Gates 67200 Cells 420MHz 1.5V 724-FCBGA | Intel
EP2A70B724I7 ObsoletePagsanggunian na paghahambing
| Parametro | EP2A70B724C8N | EP2A70B724I7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX II (EP2A70) | — |
| Family | FPGA (PLD) | APEX II |
| System Gates | 3,000,000 (3 M) | — |
| Logic Elements / Cells | 67,200 | — |
| Macrocells | 16 | — |
| Product Terms | 32 | — |
| Propagation Delay | 2.49 ns | — |
| Maximum Internal Clock Frequency | 281 MHz | — |
| Maximum Clock Frequency (fMAX) | 1694.91 MHz | — |
| Process Technology | 0.15 um CMOS, SRAM-based | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | — |
| Architecture | PLA-type / LUT-based | — |
| Package Type | FCBGA-724 (square) | — |
| Number of Pins / Balls | 724 | — |
| Terminal Pitch | 1.270 mm | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Maximum User I/O | 536 | — |
| Manufacturer | — | Intel (formerly Altera) |
| Logic Elements | — | 67200 |
| Maximum System Gates | — | 3 M |
| Embedded Memory | — | [DATA_NEEDED: ESB bits - 429 Kb or similar] |
| Maximum User I/O Pins | — | approximately 422 (724-pin FCBGA) |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltages Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V |
| PLL Blocks | — | 4 |
| True-LVDS Channels | — | 8 |
| Maximum Internal Frequency | — | 420 MHz |
| Packhaging | — | 724-pin FCBGA (FineLine BGA) |
| Operating Temperature Grade | — | Industrial (-40 C to +100 C case) |
| Configuration Interface | — | JTAG (IEEE 1149.1) / IEEE 1532 ISP |
| Tindminan RoHS | — | [DATA_NEEDED: not stated in provided data] |