EP2A70B724C9 vs EP2A70B724C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A70B724C9 sa pamamagitan ng Altera at EP2A70B724C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A70B724C9 | EP2A70B724C7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II (EP2A70) |
| Logic Elements | 67200 | — |
| Embedded Memory (bits) | 1146880 | — |
| User I/O Count | 540 | — |
| Packhaging | 724-BBGA, FCBGA (FineLine BGA) | 724-pin FCBGA (Flip-Chip BGA) |
| Process Technology | 0.15 um all-layer copper (up to 8 metal layers) | — |
| LVDS Channels | Up to 8 LVDS pairs at 1 Gbps | — |
| I/O Standards Supported | True-LVDS, LVPECL, PCML, HyperTransport | — |
| Embedded Memory Type | ESB (synchronous, self-timed WE, true dual-port / simple dual-port / single-port) | — |
| PLLs | Up to 4 | — |
| Speed Grade | C9 (commercial, speed bin 9) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | 0 °C to +85 °C (Commercial) |
| Supply Voltage (core) | 1.5 V | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Non-compliant (per IC-Components listing) | [DATA_NEEDED: RoHS status] |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Technology | — | 0.15 µm CMOS |
| System Gates | — | 3,000,000 |
| Logic Cells / Logic Elements | — | 67,200 |
| Maximum Internal Frequency | — | 420 MHz |
| Propagation Delay (typ.) | — | 2.17 ns |
| User I/O Pins | — | 536 |
| Macrocells (memory blocks reference) | — | 16 |
| Core Supply Voltage | — | 1.5 V nominal |
| I/O Supply Voltage | — | MultiVolt (1.5V / 1.8V / 2.5V / 3.3V / 5V tolerant) |
| Ball Pitch | — | 1.27 mm |
| Seated Height | — | 3.5 mm |
| Configuration Method | — | JTAG, Passive Serial (PS), Fast Passive Parallel (FPP) |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Embedded Memory | — | Embedded System Blocks (ESBs) - dual-port RAM / ROM / CAM |