EP2A70F1508C9N vs EP2A70F1508I8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A70F1508C9N sa pamamagitan ng Altera at EP2A70F1508I8 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2A70F1508C9N | EP2A70F1508I8 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Series | EP2A70 | — |
| Logic Elements / Cells | 67200 | — |
| System Gates | 3M | 3,000,000 |
| Embedded Memory Bits | 1146880 | — |
| Maximum User I/O | 1060 | — |
| Number of PLLs | 4 | — |
| Core Voltage | 1.5 V (1.425 V to 1.575 V) | 1.5 V |
| Operating Frequency | 198 MHz | — |
| Process Technology | 0.15 um CMOS | — |
| Package Type | 1508-ball FC-FBGA (Flip-Chip Fine-pitch BGA) | — |
| Package Pin Count | 1508 | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Operating Temperature Grade | Commercial | — |
| Configuration Method | JTAG, Passive Serial, Active Serial | — |
| Tindminan RoHS | Unknown - legacy part, verify with supplier | [DATA_NEEDED: per lot/date code] |
| JTAG (IEEE 1149.1) | Supported | — |
| Technology | — | 0.15 µm CMOS SRAM |
| Logic Elements (Cells) | — | 67,200 |
| Embedded System Blocks (ESBs) | — | 672 (max) |
| Embedded RAM Bits | — | 1,140,480 bits |
| Phase-Locked Loops (PLLs) | — | 4 |
| Maximum User I/O Pins | — | [DATA_NEEDED: max user I/O count per datasheet] |
| LVDS Data Rate | — | Up to 840 Mbps |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, SSTL, LVDS, LVPECL |
| Packhaging | — | FC-FBGA-1508 (FineLine BGA) |
| Temperature na Operasyon | — | -40 °C to +85 °C (Industrial) |
| Configuration Mode | — | Passive Serial, Passive Parallel, JTAG |
| Level ng MSL | — | 3 |
| Peak Reflow Temperature | — | 220 °C |