EP2AGX125EF35I3G vs EP2AGX125EF35C4G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGX125EF35I3G sa pamamagitan ng Intel at EP2AGX125EF35C4G sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2AGX125EF35I3G - Arria II GX FPGA, 118K LE, 452 I/O | Intel
EP2AGX125EF35I3G ⚠ Huling PagbiliIntel
EP2AGX125EF35C4G - Arria II GX FPGA, 118K LEs, 1152-FCBGA | Intel
EP2AGX125EF35C4G ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2AGX125EF35I3G | EP2AGX125EF35C4G |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Series | Arria II GX | — |
| Logic Elements | 118143 LE | 118,143 |
| Adaptive Logic Modules (ALMs) | 49640 ALM | — |
| Embedded Memory | 7.93 Mbit | — |
| Total RAM Bits | 8315904 bit | — |
| Number of I/O | 452 | — |
| Packhaging / Kaso | 1152-BBGA, FCBGA | — |
| Style ng Pagpapasok | SMD/SMT | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | 0C to +85C (Commercial) |
| Speed Grade | I3 | C4 |
| Process Node | 40 nm | — |
| Packaging | Tray | — |
| Tindminan RoHS | Compliant | Compliant |
| Lead Free | Yes | — |
| Transceivers | Up to 8 SERDES channels (per family) | — |
| Family | — | Arria II GX |
| Embedded Memory Bits | — | 8,315,904 |
| Memory Blocks (M9K) | — | [DATA_NEEDED: M9K count] |
| Hardware Multipliers (18x18) | — | 452 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceiver Channels | — | 12 |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| PCI Express Hard IP | — | Gen1/Gen2 x1/x4/x8 |
| Core Voltage | — | 0.9 V |
| User I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Maximum User I/O | — | [DATA_NEEDED: max user I/O count] |
| Process Technology | — | 40 nm |
| Packhaging | — | 1152-ball FC-FBGA (Flip-Chip) |
| Uri ng Pagpapasok | — | Surface Mount |
| Configuration Method | — | SRAM-based, PS/FPP/JTAG |
| Lead-Free | — | Yes |