EP2AGX190FF35C5G vs EP2AGX190FF35C4G Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGX190FF35C5G sa pamamagitan ng Intel at EP2AGX190FF35C4G sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2AGX190FF35C5G - 181165 LE Arria II GX FPGA, 612 I/O, FC-FBGA-1152 | Intel / Altera
EP2AGX190FF35C5G ✓ NakahandaAltera
EP2AGX190FF35C4G - Arria II GX FPGA 190K LE | Intel | 1152-FCBGA
EP2AGX190FF35C4G ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP2AGX190FF35C5G | EP2AGX190FF35C4G |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria II GX | Arria II GX |
| Logic Elements (LE) | 181,165 | — |
| Adaptive Logic Modules (ALM) | 71,510 | — |
| Embedded Memory (M9K blocks) | 1,118 | — |
| Embedded Memory (total) | 9,594 Kbits (10,123,008 bits) | — |
| MLAB Memory | 1.2 Mbits | — |
| DSP Blocks (18x18 multipliers) | 840 | — |
| Transceivers | 8 channels | — |
| Transceiver Data Rate (max) | 3.75 Gbps | — |
| Maximum User I/O Pins | 612 | — |
| PLLs | 4 | — |
| Memory Controllers | 4 (hard IP) | — |
| Core Voltage | 0.9 V | — |
| I/O Voltage Support | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Node | 40 nm | — |
| Packhaging | 1152-ball FC-FBGA (FF35) | 1152-BBGA, FCBGA (35 mm) |
| Speed Grade | C5 (commercial, mid-performance) | C4 |
| Operating Temperature (commercial) | 0C to +85C | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | Compliant | Compliant |
| Logic Elements | — | 181,165 |
| Equivalent Logic Elements | — | 190,000 |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| Embedded Memory (bits) | — | 10,177,536 |
| Embedded Memory (M20K blocks) | — | [DATA_NEEDED: M20K block count] |
| Embedded 18x18 Multipliers | — | 612 |
| Transceiver Channels | — | 12 (up to 6.375 Gbps) |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Hard PCIe Gen2 Blocks | — | Yes (2) |
| User I/O Pins (maximum) | — | [DATA_NEEDED: user I/O count] |
| Process Technology | — | 40 nm low-power CMOS |
| Operating Temperature Grade | — | Commercial (0C to +85C) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | Yes |
| Development Tool | — | Quartus II (legacy) |