EP2AGZ350HF40C2N vs EP2AGZ350HF40I2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGZ350HF40C2N sa pamamagitan ng Altera at EP2AGZ350HF40I2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2AGZ350HF40C2N | EP2AGZ350HF40I2N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Arria II GZ | Arria II GZ |
| Logic Elements | 350,000 | 350000 |
| Embedded Memory | approximately 20 Mbits | [DATA_NEEDED: Mbits] |
| DSP Blocks | Dedicated 18x18 multipliers | [DATA_NEEDED: DSP block count] |
| Transceivers | Up to 16 channels | Embedded multi-gigabit transceivers |
| Transceiver Data Rate | Up to 6.375 Gbps | — |
| Packhaging | 1517-ball FCBGA (HF40), 40 mm x 40 mm | 1517-pin FBGA (HF40) |
| Speed Grade | C2 (commercial) | — |
| Temperature na Operasyon | 0C to +85C (commercial, per N suffix) | -40C to +100C (Industrial) |
| Process Node | 40 nm low-power | [DATA_NEEDED: process node nm] |
| I/O Standards | LVDS, LVCMOS, SSTL, HSTL, differential standards | — |
| External Memory Support | DDR3, QDR II+, RLDRAM II | — |
| Configuration Method | Quartus II design suite, JTAG, passive/active serial | — |
| Tindminan RoHS | Compliant (per product listing) | Compliant |
| Uri ng Pagpapasok | Surface Mount (FCBGA) | Surface Mount (BGA) |
| Supply Voltage (Core) | — | [DATA_NEEDED: core Vcc] |
| Max Transceiver Data Rate | — | 6.375 Gbps |
| User I/O Banks | — | [DATA_NEEDED: bank count] |
| Maximum User I/O | — | [DATA_NEEDED: max user I/O count] |
| Lead-Free | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| AEC-Q100 | — | not_applicable |