EP2C35F484C7 vs EP2C35U484C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C35F484C7 sa pamamagitan ng Intel at EP2C35U484C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2C35F484C7 | EP2C35U484C6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Series | Cyclone II | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 33,216 LE | 33,216 |
| Total Memory Bits | 483,840 bits | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Embedded Multipliers (18x18) | 35 | — |
| Maximum User I/O | 322 | — |
| Number of PLLs | 4 | 4 |
| Global Clock Networks | 16 | — |
| Process Technology | 90 nm CMOS, 1.2 V core | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Temperature na Operasyon | 0 C to 85 C (Commercial) | 0C to +85C (commercial) |
| Packhaging | 484-pin FBGA (FineLine BGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Modes | JTAG, Passive Serial (PS), Active Serial (AS) | — |
| I/O Standards | LVDS, LVTTL, LVCMOS, SSTL, HSTL | — |
| External Memory Support | DDR, DDR2, QDRII SRAM | — |
| Lead-Free / RoHS | Lead-Free (per 'N' suffix not present; C7 = commercial temp) | — |
| Family | — | Cyclone II |
| Total RAM Bits | — | 483,840 |
| Number of LABs/CLBs | — | 2,076 |
| User I/O Count | — | 322 |
| Embedded Multipliers | — | 35 (18x18) |
| Speed Grade | — | C6 |
| Package Type | — | 484-FBGA (U484, FineLine BGA) |
| Package Dimensions | — | 19 mm x 19 mm |
| Ball Pitch | — | 1.0 mm |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Configuration Interface | — | Passive Serial / Active Serial / JTAG |
| DSP Block Count | — | 35 columns |