EP2C50F672C8N vs EP2C50F672I8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C50F672C8N sa pamamagitan ng Intel at EP2C50F672I8N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2C50F672C8N - Cyclone II FPGA, 50K LE, 672-BGA | Intel / Altera
EP2C50F672C8N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2C50F672C8N | EP2C50F672I8N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | Cyclone II | — |
| Number of Logic Elements | 50,528 | — |
| Number of Logic Array Blocks (LABs) | 4,608 | — |
| Total RAM Bits | 594,432 | — |
| Number of I/O | 450 | — |
| Number of User I/O Banks | 8 (per family architecture) | — |
| Number of PLLs | 4 | — |
| Number of DLLs | 2 | — |
| Embedded 18x18 Multipliers | 86 | — |
| Core Voltage | 1.2 V | — |
| Packhaging | 672-FBGA (FineLine BGA) | — |
| Package Body Size | 27 mm x 27 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface mount BGA |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Speed Grade | C8 | — |
| Process Technology | 90 nm low-k CMOS | — |
| Configuration | JTAG + serial/parallel | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status from datasheet] | unknown |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Device Family | — | Cyclone II |
| Logic Technology | — | CMOS |
| Logic Elements | — | 50,528 |
| Embedded Memory | — | 594,432 bits |
| User I/O | — | 450 |
| Volte ng Pagbibigay | — | 1.2 V |
| Package Type | — | 672-BGA |
| Package Designation | — | FBGA-672 |
| Bilang ng Pin | — | 672 |
| Ordering Temperature Grade | — | I8N industrial grade designation |
| Configuration Method | — | [DATA_NEEDED: configuration mode] |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Embedded Multipliers | — | [DATA_NEEDED: embedded multiplier count] |
| Phase-Locked Loops | — | [DATA_NEEDED: PLL count] |
| Global Clock Networks | — | [DATA_NEEDED: global clock network count] |
| REACH Status | — | unknown |