EP2C50U484C7N vs EP2C50U484C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2C50U484C7N sa pamamagitan ng Intel at EP2C50U484C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2C50U484C7N | EP2C50U484C6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Series | Cyclone II | Cyclone II |
| Family Name | Cyclone II FPGA | — |
| Logic Elements | 50,528 | 50,528 |
| Number of Logic Cells | 3,158 (per digchips) | — |
| Number of LABs | [DATA_NEEDED: LAB count] | — |
| Maximum System Gates | 594,432 | — |
| Number of Registers | 50,528 | — |
| Total Embedded RAM | 234 Kbits (M4K blocks) | — |
| Embedded Multipliers | 86 (18x18) | — |
| PLLs | 4 | 4 |
| User I/O Pins | 294 | 294 |
| Packhaging | 484-FBGA (UBGA-484), 1.0 mm pitch | 484-pin UBGA (Ultra FineLine BGA) |
| Temperature na Operasyon | 0C to 85C (commercial, C-grade) | 0C to +85C (Commercial) |
| Supply Voltage Core (VCCINT) | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS, low-k dielectric |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Lead Free | — |
| Level ng MSL | 3 | — |
| Speed Grade | C7 (7 ns pin-to-pin delay) | — |
| Logic Array Blocks (LABs) | — | 3,158 |
| Total Memory Bits | — | 594,432 |
| Embedded Multiplier Blocks (DSP) | — | 250 (18x18) |
| Maximum User I/O | — | 315 |
| Core Voltage | — | 1.2 V |
| Internal Frequency | — | up to 500 MHz |
| Configuration Mode | — | JTAG, Active Serial (AS), Passive Serial (PS) |
| Lead Free | — | Yes |
| Tindminan RoHS | — | Compliant |