EP2S130F1020C4 vs EP2S130F1020C5N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F1020C4 sa pamamagitan ng Intel at EP2S130F1020C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2S130F1020C4 EP2S130F1020C5N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Stratix II Stratix II
Logic Elements 132,540 132,540
Process Technology 90 nm 90 nm
Core Voltage 1.2 V —
Packhaging 1020-ball FC-FBGA 1020-ball FC-FBGA (33x33 mm)
User I/O Count 742 —
Maximum Internal Frequency 711.24 MHz 609.76 MHz
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon Commercial (0C to +85C) - grade 'C' Commercial (0C to +85C, C5 grade)
Speed Grade C4 —
Uri ng Memory Embedded SRAM blocks (Stratix II) —
DSP Blocks Embedded multipliers (Stratix II TriMatrix) —
PLLs Yes (Stratix II enhanced PLL + fast PLL) 4 (typical Stratix II feature)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free status]
Adaptive Logic Modules (ALMs) — 6627 LABs (per Jotrin listing)
Total Memory Bits — 6,747,840 bits
User I/Os — 734
Core Supply Voltage (VCCINT) — 1.15 V to 1.25 V
Temperature Grade — C5 (other - per Partstack)
Global Clock Networks — 16 (typical Stratix II feature)
Configuration Method — Serial/Parallel via Quartus II (typical Stratix II)
Country of Origin — Republic of Korea (per GlobalSpec)
ECCN — 3A001.a.7.a (per GlobalSpec)
Estimated EOL Date — 2023 (per GlobalSpec)

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