EP2S130F1020C4RB vs EP2S130F1020C5N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F1020C4RB sa pamamagitan ng Intel at EP2S130F1020C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2S130F1020C4RB EP2S130F1020C5N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Device Family Stratix II (EP2S130) —
Logic Elements 132,540 132,540
Adaptive Logic Modules (ALMs) 53,016 6627 LABs (per Jotrin listing)
User I/O Pins 742 —
Packhaging 1020-ball FBGA 1020-ball FC-FBGA (33x33 mm)
Total RAM Bits 6,747,000 —
18x18 Multipliers 152 (per device family) —
Transceiver Channels 12 (up to 6.375 Gbps per family) —
Speed Grade C4 —
Core Voltage 1.2 V (typical) —
Process Technology 90 nm 90 nm
Temperature na Operasyon Commercial (0C to +85C) Commercial (0C to +85C, C5 grade)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Tindminan RoHS [DATA_NEEDED: confirm RoHS class] [DATA_NEEDED: rohs status]
Lead-Free [DATA_NEEDED: confirm lead-free status] [DATA_NEEDED: lead-free status]
Family — Stratix II
Total Memory Bits — 6,747,840 bits
User I/Os — 734
Core Supply Voltage (VCCINT) — 1.15 V to 1.25 V
Maximum Internal Frequency — 609.76 MHz
Temperature Grade — C5 (other - per Partstack)
PLLs — 4 (typical Stratix II feature)
Global Clock Networks — 16 (typical Stratix II feature)
Configuration Method — Serial/Parallel via Quartus II (typical Stratix II)
Country of Origin — Republic of Korea (per GlobalSpec)
ECCN — 3A001.a.7.a (per GlobalSpec)
Estimated EOL Date — 2023 (per GlobalSpec)

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