EP2S130F1020C5N vs EP2S130F1020C4RB Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F1020C5N sa pamamagitan ng Intel at EP2S130F1020C4RB sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S130F1020C5N | EP2S130F1020C4RB |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Stratix II | — |
| Logic Elements | 132,540 | 132,540 |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | 53,016 |
| Total Memory Bits | 6,747,840 bits | — |
| User I/Os | 734 | — |
| Process Technology | 90 nm | 90 nm |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Maximum Internal Frequency | 609.76 MHz | — |
| Packhaging | 1020-ball FC-FBGA (33x33 mm) | 1020-ball FBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | Commercial (0C to +85C, C5 grade) | Commercial (0C to +85C) |
| Temperature Grade | C5 (other - per Partstack) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: confirm RoHS class] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: confirm lead-free status] |
| PLLs | 4 (typical Stratix II feature) | — |
| Global Clock Networks | 16 (typical Stratix II feature) | — |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | — |
| Country of Origin | Republic of Korea (per GlobalSpec) | — |
| ECCN | 3A001.a.7.a (per GlobalSpec) | — |
| Estimated EOL Date | 2023 (per GlobalSpec) | — |
| Device Family | — | Stratix II (EP2S130) |
| User I/O Pins | — | 742 |
| Total RAM Bits | — | 6,747,000 |
| 18x18 Multipliers | — | 152 (per device family) |
| Transceiver Channels | — | 12 (up to 6.375 Gbps per family) |
| Speed Grade | — | C4 |
| Core Voltage | — | 1.2 V (typical) |