EP2S130F780C5 vs EP2S130F780C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S130F780C5 sa pamamagitan ng Intel at EP2S130F780C4 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S130F780C5 | EP2S130F780C4 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Logic Array Blocks (LABs) | 6627 | 6,627 |
| User I/O Count | 534 | — |
| Embedded Memory (bits) | 6,737,280 | — |
| Embedded 18x18 Multipliers | 252 | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage (VCCINT) | 1.15 V to 1.25 V (typ. 1.2 V) | — |
| Internal Clock Frequency (max) | 609.76 MHz | — |
| Speed Grade | C5 | C4 (commercial) |
| Temperature na Operasyon | 0 C to +85 C (TJ) | — |
| Packhaging | 780-FBGA (FC-FBGA), 29 mm x 29 mm | 780-ball FC-FBGA (flip-chip) |
| Lead-Free / RoHS | Lead Free / RoHS Compliant | — |
| Configuration Interface | JTAG (IEEE 1149.1) + Passive Serial / Fast Passive Parallel | — |
| DSP Performance | Up to ~1.4 GMACs (per family datasheet) | — |
| User I/O Pins | — | 534 |
| Internal Frequency (max) | — | 717 MHz |
| Core Voltage | — | 1.2 V |
| Package Code | — | F (FBGA-780) |
| Package Body Size | — | 40 x 40 mm |
| Ball Pitch | — | 1.0 mm |
| Terminal Form | — | Ball (BGA) |
| Uri ng Pagpapasok | — | Surface Mount |
| Tindminan RoHS | — | Lead-free (per datasheet) |