EP2S15F484C4N vs EP2S30F484C4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S15F484C4N sa pamamagitan ng Intel at EP2S30F484C4N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S15F484C4N | EP2S30F484C4N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Stratix II | — |
| Family Name | Stratix II | — |
| Number of Logic Elements / Cells | 15600 | — |
| Number of LABs / CLBs | 780 | — |
| Total RAM Bits | 419328 | 1,369,728 |
| Number of I/O | 342 | — |
| Number of Gates | [DATA_NEEDED: number of gates] | — |
| Supply Voltage - Core | 1.15 V to 1.25 V | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Speed Grade | C4 | C4 (commercial) |
| Packhaging / Kaso | 484-BBGA, FCBGA | — |
| Package Dimensions | 23 x 23 mm | — |
| Process Node | 90 nm | — |
| PLL Count | 6 | — |
| Embedded Multipliers | Up to 156 (18x18) | — |
| Maksimum na Taktiko ng Oras | 717 MHz (PLL) | — |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG | — |
| Lead Free / RoHS | [DATA_NEEDED] | — |
| Level ng MSL | 3 (168 hours) | [DATA_NEEDED: MSL moisture sensitivity level] |
| Family | — | Stratix II |
| Logic Elements | — | 33,880 |
| Logic Array Blocks (LABs) | — | 1,694 |
| User I/Os | — | 342 |
| Packhaging | — | 484-ball FC-FBGA |
| Package Pin Count | — | 484 |
| Process Technology | — | 90 nm CMOS |
| Core Voltage | — | 1.2 V |
| Maximum Internal Frequency | — | 711.24 MHz |
| Temperature Grade | — | Commercial |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free / RoHS status] |