EP2S60F484C3 vs EP2S60F484C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S60F484C3 sa pamamagitan ng Altera at EP2S60F484C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S60F484C3 | EP2S60F484C3N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | Stratix II | — |
| Manufacturer | Altera (now Intel FPGA) | — |
| Logic Elements | 60,440 | 60,440 |
| Adaptive Logic Modules (ALMs) | 24,176 | — |
| LABs/CLBs | 3,022 | — |
| Total RAM Bits | 2,544,192 | — |
| User I/O Count | 334 | — |
| Packhaging | 484-BBGA, FCBGA (FBGA-484) | 484-BGA (F484), 1.0 mm pitch |
| Package Size | 23 x 23 mm, 1.0 mm pitch | — |
| Core Voltage | 1.2 V | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS, 1.2 V core |
| Speed Grade | C3 | -3 (fastest commercial) |
| Temperature na Operasyon | 0C to +85C (commercial) | — |
| Number of PLLs | 12 (Stratix II typical) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Total Multipliers | 12 (9-bit embedded multiplier blocks) | — |
| Family | — | Stratix II |
| Adaptive LUTs (ALUTs) | — | 48,352 |
| Embedded Memory (TriMatrix) | — | 2,544 Kbits (M4K + M512 + M-RAM) |
| Embedded DSP Blocks | — | 12 (48 GMACs at 450 MHz) |
| Maximum User I/O Pins | — | 334 |
| Operating Temperature (Commercial) | — | 0C to +85C (TJ) |
| Supply Voltage VCCINT | — | 1.2 V nominal |
| Configuration Modes | — | FPP, AS, PS, JTAG |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Lead-Free | — | Yes |