EP2S60F484C4N vs EP2S60F484C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S60F484C4N sa pamamagitan ng Intel at EP2S60F484C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S60F484C4N | EP2S60F484C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | Stratix II | — |
| Family | Stratix II FPGA | Stratix II |
| Logic Elements (LE) | 60,440 | — |
| Adaptive Logic Modules (ALM) | 30,220 | — |
| Embedded Memory (Bits) | 2,544,192 | — |
| DSP Blocks (18x18 Multipliers) | 36 | — |
| Maximum User I/O | 334 | — |
| User I/O Banks | [DATA_NEEDED: User I/O Banks] | — |
| PLLs | Up to 12 | — |
| Process Technology | 90 nm CMOS | 90 nm CMOS, 1.2 V core |
| Core Supply Voltage | 1.2 V | — |
| Maximum Internal Clock Frequency | 711.24 MHz | — |
| Packhaging | 484-Ball FBGA (FineLine BGA) | 484-BGA (F484), 1.0 mm pitch |
| Uri ng Pagpapasok | Surface Mount | — |
| Operating Temperature Grade | Commercial (C4) | — |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | FPP, AS, PS, JTAG |
| Tindminan RoHS | [DATA_NEEDED: RoHS Status] | Compliant |
| Lead-Free | [DATA_NEEDED: Lead-Free] | Yes |
| Logic Elements | — | 60,440 |
| Adaptive LUTs (ALUTs) | — | 48,352 |
| Embedded Memory (TriMatrix) | — | 2,544 Kbits (M4K + M512 + M-RAM) |
| Embedded DSP Blocks | — | 12 (48 GMACs at 450 MHz) |
| Maximum User I/O Pins | — | 334 |
| Speed Grade | — | -3 (fastest commercial) |
| Operating Temperature (Commercial) | — | 0C to +85C (TJ) |
| Supply Voltage VCCINT | — | 1.2 V nominal |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |