EP2S60F672C5 vs EP2S60F672I4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S60F672C5 sa pamamagitan ng Intel at EP2S60F672I4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S60F672C5 | EP2S60F672I4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix II | Stratix II FPGA |
| Device Family | Stratix II FPGA | — |
| Logic Elements | 60,440 | — |
| Configurable Logic Blocks (CLBs) | 24,176 | — |
| Total RAM Bits | 2,544,192 bits | 2,544,192 |
| Maximum User I/Os | 492 | — |
| Operating Frequency | Up to 609.76 MHz | — |
| Core Voltage | 1.2 V | 1.2 V |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Packhaging | 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C5 suffix) | Industrial (-40C to +100C) |
| Hanay ng Temperature na Operasyon | 0°C to +85°C | — |
| Number of PLLs | 4 | — |
| DSP Blocks | 12 (dedicated 18 × 18 multipliers) | — |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X | — |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial | — |
| Tindminan RoHS | Non-RoHS (legacy product, pre-RoHS production runs) | Compliant |
| Series | — | Stratix II |
| Logic Elements (LE) | — | 60,440 |
| Logic Array Blocks (LAB) | — | 3,022 |
| User I/O Count | — | 492 |
| Maximum Internal Frequency | — | 711.24 MHz |
| Package Type | — | 672-ball FC-FBGA (Fine-pitch Chip-scale BGA) |
| Speed Grade | — | -4 |
| Lead-Free | — | Yes |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |