EP2S90F1020C5N vs EP2S130F1020C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S90F1020C5N sa pamamagitan ng Intel at EP2S130F1020C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S90F1020C5N | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Series | Stratix II | — |
| Family | Stratix II (EP2S90) | Stratix II |
| Process Node | 90 nm | — |
| Logic Elements (LEs) | 90,960 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | 6627 LABs (per Jotrin listing) |
| Embedded Memory (TriMatrix) | 4,520,488 bits | — |
| Embedded Multipliers (18x18) | 12 (DSP blocks) | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| User I/Os | 758 | 734 |
| Maximum User I/O Pins | 758 | — |
| Packhaging | 1020-ball FBGA (FineLine BGA) | 1020-ball FC-FBGA (33x33 mm) |
| Speed Grade | -5 (commercial, faster bin) | — |
| Temperature na Operasyon | 0C to +85C (commercial) | Commercial (0C to +85C, C5 grade) |
| Supply Voltage (Core) | [DATA_NEEDED: Vcore, typically 1.2 V] | — |
| Lead-Free / RoHS | Lead Free / RoHS Compliant | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Design Tool | Quartus II (legacy, Altera) | — |
| Logic Elements | — | 132,540 |
| Total Memory Bits | — | 6,747,840 bits |
| Process Technology | — | 90 nm |
| Core Supply Voltage (VCCINT) | — | 1.15 V to 1.25 V |
| Maximum Internal Frequency | — | 609.76 MHz |
| Temperature Grade | — | C5 (other - per Partstack) |
| Tindminan RoHS | — | [DATA_NEEDED: rohs status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| PLLs | — | 4 (typical Stratix II feature) |
| Global Clock Networks | — | 16 (typical Stratix II feature) |
| Configuration Method | — | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | — | Republic of Korea (per GlobalSpec) |
| ECCN | — | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | — | 2023 (per GlobalSpec) |