EP2SGX130GF1508C3 vs EP2SGX130GF40C3NES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2SGX130GF1508C3 sa pamamagitan ng Intel at EP2SGX130GF40C3NES sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera
EP2SGX130GF40C3NES ObsoletePagsanggunian na paghahambing
| Parametro | EP2SGX130GF1508C3 | EP2SGX130GF40C3NES |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements | 132,540 | 132540 |
| Logic Array Blocks (LABs) | 6,627 | 7047 |
| Total Memory Bits | 6,748,860 | — |
| Maximum User I/O | 734 | — |
| Number of I/O Banks | 12 | — |
| Transceiver Channels | Up to 20 | 4 to 20 (per device family configuration) |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Core Voltage | 1.2 V | 1.2 V |
| Operating Temperature Grade | Commercial (C3 speed grade) | Commercial Extended |
| Packhaging | 1508-ball FBGA (FCBGA) 40 x 40 mm, 1.0 mm pitch | 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) |
| Maximum Internal Frequency | 717 MHz | 778.82 MHz |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | Contains lead / RoHS non-compliant | Lead-free compliant (per package code MS-034AAU-1) |
| Maximum Transceiver Data Rate | — | 6.375 Gbps |
| Transceiver Feature | — | Embedded SERDES with Clock/Data Recovery (CRU) |
| Uri ng Memory | — | TriMatrix embedded memory (distributed RAM, block RAM, shift register) |
| Terminal Form | — | Ball (BGA) |
| Series | — | EP2SGX130 |